Posted on Friday, February 22 2019 @ 11:09 CET by Thomas De Maesschalck
Over at the International Solid State Circuits Conference in San Francisco, SK Hynix provided details about its DDR5 technology. This standard hasn't been finalized yet by JEDEC, DDR5 will aim to offer double the bandwidth and double the density of DDR4, while also delivering higher channel efficiency. The first DDR5 proucts are expected by the end of 2019. You can read all about it
at EE Times.
Dongkyun Kim, a Hynix chip designer, presented the ISSCC paper Wednesday on the Hynix DDR5 chip, a 16Gb 6.4Gb/s/pin SDRAM that runs at 1.1V and measures 76.22mm2. The device is fabricated in a 1ynm, 4-metal DRAM process.
Kim described the implementation of a modified delay-locked loop (DLL) using a phase rotator and an injection locked oscillator to reduce clock jitter and clock duty cycle distortion associated with operating at higher clock speeds. He also described other techniques used by the Hynix design team, including a write-level training method to offset clock-domain issues associated with higher speeds and a modified forward feedback equalization (FFE) circuit.
